The fabrication of microelectronic devices, such as transistors, in a SOI substrate comprises the realization of insulation trenches, for example of the STI type, that allow an electrical isolation of the active regions of the devices, made in the same SOI substrate, from each other.
The pattern of the isolation trenches made in the substrate is complementary to that of the active regions of the devices. An example of an isolation trench 8 of the STI type is shown in FIG. 1. This trench 8 is made in an SOI substrate 1 comprising a support layer 2, or thick layer, composed of semiconductor (typically of silicon) coated with a dielectric thin layer 4 called BOX (Burried OXide) and a thin layer 6, or surface layer, composed of semiconductor, here of silicon, and wherein the active regions of the devices are intended to be made. The isolation trench 8 bounds here two active regions 10a and 10b of two transistors made in the semiconductor thin layer 6. The isolation trench 8, composed of a dielectric material such as SiO2, is made through the entire thicknesses of the semiconductor thin layer 6 and of the dielectric thin layer 4, and a part of the thickness of the support layer 2.
During the fabrication of the microelectronic devices in the substrate 1, after forming the isolation trench 8, the substrate 1 usually undergoes several steps of cleaning and etching which can damage the insulation trench 8, such as cleaning steps performed with a hydrofluoric acid solution and after a gate etching or prior to silicidation or epitaxy steps. The semiconductor oxide of the isolation trench 8 is attacked by these steps and partially removed, both vertically and horizontally (see FIG. 2 onto which the dielectric material of the isolation trench 8 is partially withdrawn). Such degradations of the isolation trench 8 can lead to problems of electrical insulation between the support layer 2 and the thin layer 6, especially during the subsequent realization of electrical contacts in the vicinity of the isolation trench 8. In the example shown on FIG. 3, one of the electrical contacts 12 is intended to electrically contact a portion of the active region 10b near the isolation trench 8, this portion corresponding for example to a source or drain region of a transistor made in the active region 10b. However, in current technology nodes, given the short distance between two active regions (equal to about 50 nm in the 20 nm-node technology) which corresponds to the width of the isolation trench, a slight misalignment during the lithography made to form the electrical contact 12 can cause a shift of this electrical contact 12 on the isolation trench 8. Such a shift can also be intentional, some electrical contacts being made voluntarily overflowing on the isolation trench 8. However, given the partial withdrawal of SiO2 of the isolation trench 8, this offset can lead to a short circuit between the active region 10b formed in the semiconductor thin layer 6 and the semiconductor of the support layer 2 (on the example of FIG. 3, a part of the electrical contact 12 is placed in a recess formed by the partial removal of the dielectric material of the isolation trench 8, thus short-circuiting the thin layer 6 with the support layer 2).
To solve this problem of degradation of the insulation trenches, a solution shown in FIG. 4 is, when performing an isolation trench 15, first to cover the walls (side walls and bottom wall) of the trench with a thin layer 14 (a liner) composed of a dielectric material more resistant than the semiconductor oxide used to make the isolation trench 8, for example silicon nitride. The remaining space of the trench is then filled with a semiconductor oxide 16, like SiO2.
The parts of the SiN layer 14 forming the side walls of the isolation trench 15 strengthen the resistance of the isolation trench 15 towards the steps of cleaning and etching.
However, although this solution partially avoids degrading the isolation trench during the steps of cleaning and etching, it does not completely eliminate the risk of short circuit described above. Indeed, during the etching of the electrical contacts, it is necessary to etch a thin nitride layer (called “contact etch stop layer”), which will result in the simultaneous etching of the nitride layer 14 and thus destroy the sealing made by the nitride layer 14. In addition, when the layer 14 is composed of a high permittivity dielectric, electrical performance degradations are observed as a result of an oxygen diffusion occurring through the liner.